1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a data holding circuit such as a latch, flip flop, and SRAM and related technologies.
2. Description of the Related Art
In a mobile phone terminal, its idle state occupies most in its process flow. Therefore, in a semiconductor integrated circuit for a mobile phone terminal, reducing the leak current in the idle state is an effective measure for lowering the power consumption. Many techniques, such as power-supply control, substrate control and power cut-off have been proposed as techniques for reducing the leak current. Of these, the power cut-off technique is a technique of stopping unnecessary supply of power to circuits during the idle state of the semiconductor integrated circuit, and has a large effect on lowering leakage. However, when processing of stopping the power supply is performed, data held in the data holding circuit of the circuit disappears. Therefore, when it is necessary to save data recorded before the idle state, complicated circuitry and control operation such as for storing data in another circuit are needed; however, in this case, an additional area for storing data temporarily is required and power is consumed during processing of storing data temporarily and restoring the data. This technique is disclosed for example in literature (Takayasu Sakurai, et al., “Low-power, High-speed LSI Technology”, Realize Advanced Technology Limited, pp 64-68, 1998).
Also, even in the case of a circuit in which it is not necessary to save data recorded before the idle state, when shifting from an idle state to an operating state, it is necessary to reset data inside the circuit to a specified state, and not only does this operation require processing time, but also consumes power.
The power cut-off technique is effective in this way in reducing power consumption during the idle state of a semiconductor integrated circuit, however, data that is recorded in the internal data-holding circuit cannot be saved. The outline of this power cut-off technique is shown in FIG. 12A and FIG. 12B, taking a latch circuit as an example.
In FIG. 12A, QN1 is a first NMOS transistor, QP1 is a first PMOS transistor, QN2 is a second NMOS transistor, QP2 is a second PMOS transistor, n1 and n2 are latch nodes, VDD is a power-supply terminal, VSS is a ground terminal, and QS is a power-supply switch.
In a normal idle state, “H” or “L” data is recorded in each of the latch nodes n1, n2. In this state, a certain amount of leak current flows in the latch nodes n1, n2. When the power-supply switch QS goes OFF to cut off the power supply, the leak current that flows through the internal transistors becomes essentially zero, and power consumption by the latch circuit is reduced. However, the “H” or “L” data that is recorded by the latch nodes n1, n2 disappears. When the power-supply switch goes ON and the circuit is once again in the power-supply state, the data at the latch nodes n1, n2 differs from the desired data, and each time this operation is repeated the data randomly becomes “H” or “L”.
In order to explain this phenomenon, the construction of a normal CMOS inverter is shown in FIG. 13A. In FIG. 13A Tin is an input terminal and Tout is an output terminal. In this CMOS inverter circuit, the output state “H” or “L” is determined according to the magnitude relationship between the ON current and OFF current of the NMOS transistor and PMOS transistor constituting the inverter.
FIG. 13B shows the current characteristics of the NMOS transistor QN and PMOS transistor QP. The characteristic curve of the NMOS transistor QN is shown by the solid line, and the characteristic curve of the PMOS transistor QP is shown by the dashed line. As shown by the arrow Y1, in the NMOS transistor QN, the ON current ION—N is always greater than the OFF current IOFF—N, and as shown by the arrow Y2, in the PMOS transistor QP, the ON current ION—P is always greater than the OFF current IOFF—P. Therefore, the potential of the output terminal Tout is fixed to the source voltage of the transistor in the ON state that is set according to the input signal. Also, as shown by the arrow Y3, over the entire range of the power-supply voltage VDS, the ON current ION—N, ION—P is greater than the OFF current IOFF—N, IOFF—P. However, when the power-supply voltage is near 0V, the ON current and OFF current of the NMOS transistor QN and PMOS transistor QP become nearly equal, so in this area, the output terminal of the inverter becomes unstable.
As explained above, when the power supply to a latch circuit is cut off, data is lost, so the power cut-off technique cannot be used for circuits in which data must be saved. Also, even in the case of circuits in which data does not need to be saved, data reset operation is necessary for setting the initial state, which is disadvantageous from the aspect of time and power consumption.